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Embedded Systems 8 Elektronik International 2020 accumulator designated A 8051 8080 and 6502 were typical of this CPU type Then word sizes increased to 16 and 32 bits The RISC concept came along where all registers were the same typically called R0R15 with 16 generalpurpose registers All instructions from the first ARM processor were 32-bit That way the CPU may have stayed simple but the programs became enormous because so many instructions were needed each using 4 bytes Take the following line of code for example Cnt++ Its sole purpose is to increment a global variable An ARM processor takes four instructions for this action LDR R0 =Cnt load address in R0 Note that the address of Cnt is stored relative to the program counter and takes another 4 bytes LDR R1 R0 ADD R1 R1 #1 STR R1 R0 On an ARM core in ARM mode that meant 20 bytes An 8051 could do this in 2 bytes in IRAM und 6 bytes in XRAM Note that this already takes 1 or 2 bytes for the address ARM realized the problem and improved code density by introducing Thumb where all instructions except for a BL subroutine call are 2-byte It wasnt easy to access all registers and some instructions simply arent available In many cases it took more instructions on average perhaps 40% more to implement the same functionality in Thumb mode But given the fact that the instructions were only half the size this still meant a smaller program 140% 2 = 70% in other words 30% smaller without considering the literal In the case of the instructions named above theyre all available in Thumb mode so that code size would shrink from 4*4 + 4 = 20 bytes to 4*2 + 4 = 12 bytes ARM also added some more instructions like PUSHM making it possible to shift a number of register contents to the stack by a single instruction The same applies to POPM which can take registers from the stack The register list is flexible and can include the program counter so that returning a function is often a single POPM instruction Another example is the introduction of a call named BLX branch link with mode exchange The drawback of Thumb mode was that the processor could change mode and only execute Thumb instructions Switching modes needed a special BX instruction branch with mode switch ARM recognized the potential for improvement and introduced Thumb-2 a mixture of 2-byte and 4-byte instructions It no longer took a mode switch and the code density of Thumb-2 is acceptable even if you have processors with higher code density like Renesas RX But what about code density in RISC-V? Ill tell you straight off its a catastrophe RISC-Vdesign is very similar to the MIPS CPU 32 registers the first always 0 There are no flags and all instructions are 32-bit RISC-Vis unfortunately similar to a design 20 to 30 years old So in most cases more instructions are needed than in competing architectures That means a fair amount of code not really suitable for smaller devices like microcontrollers in embedded systems Now look at the price with no flags like carry NO FLAGS RISC-Vhas no flags no carry no zero and no sign flags Even old 8-bit processors had them Meaning that it takes more instructions for many operations Lets have a look at a piece of code that just adds two 64-bit values int unsigned long long sum unsigned long long x unsigned long long y { return x + y } From an ARM Cortex-Mwe need two instructions taking up 6 bytes of memory R1 R0 x R3 R2 y Return R1 R0 adds r0 r0 r2 add low 32 bits and set carry adc w r1 r3 r1 add top 32 bits incl carry bx lr ARM version of RET RISC-Vtakes five instructions a total of 12 bytes A1 A0 x A3 A2 y Return A1 A0 mv a5 a0 a5 = a0 add a0 a0 a2 add low 32 bits sltu a5 a0 a5 set less than no sign a5 = a0 < a5 ? 1 0 a5 acts as carry flag add a1 a1 a3 add top 32 bits add a1 a1 a5 add carry ret The RISC-Vcode needs five instructions and 12 bytes while Thumb-2 code does it with only two instructions for 6 bytes So what can you do to improve code density in RISC-V ➔ introduce a flag register and ensure that flags are set by all relevant operations ➔ introduce operations that use flags for example ADC Add with Carry ➔ introduce PUSHM POPM ➔ introduce load and store with postincrement for example LDR Rx Ry++ ➔ insert a shift register window so that no push and pop is necessary for function input and output RV32E TO THE RESCUE? SORRY NO WAY RV32E is the embedded version of the RISC-V CPU The main difference is that the number of generalpurpose registers