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Power SemiconductorS advancements to deliver even better perfor mance By reducing the cell pitch and refining channel properties significant improvements in device performance have been achieved moreover an enhanced control over drift region properties enables more precise man agement of the device’s behavior through meticulous optimization of the chip design for example the junction termination the active area loss has been minimized the result is a nextgeneration 400 V Sic moSFet that sets a new standard for performance reliability and efficiency enabling the devel opment of more innovative and sustainable power electronic systems By combining the coolSic 400 Vwith a low inductance package like toLeadless toLL designers can create optimized PcB printed circuit board layouts that fully leverage the device’s exceptional switching performance the high c oss linearity and commutationro bust body diode with low Qfr work together to minimize VdS overshoots and ringing ensuring stable switching waveforms that are virtually independent of operating temperature and load current the excellent switching Foms translate to high switching speeds resulting in minimized switching and deadtime losses which result in improvement in efficiency and power density with good emi electromag netic interference performance Putting coolSic 400 Vto the test Performance evaluation in a totempole Power Factor correction the bridgeless 2level 2L totempole PFc topology is the stateoftheart solution for highefficiency and high powerdensity designs eliminating dioderelated losses and offering good performance with efficiencies reaching up to 99 percent this versatile topology can be operated in various control modes including continuous current mode ccm discontinuous current mode dcm critical current mode crcm and triangular current mode tcm and is inherently capable of bidirectional power flow However to take efficiency and power density to the next level in systems with input voltages ranging from 180 to 350 V Ac multilevel topologies are the way forward one promising approach to further boost power density is the 3level 3L flying capacitor ccm totempole topology as illustrated in Figure 1 By connecting two devices in series in the highfrequency HF leg for the same dc output voltage the blocking voltage requirement for each device is halved resulting in signifi cantly reduced switching losses Additionally the voltage swing across the inductor is also halved when combined with the benefits of “series interleaving” inherent to the flying capa citor topology the effective switching frequency is doubled compared to the device switching frequency the higher effective switching fre quency combined with a lower voltage swing across the inductor allows for a significant reduction 1 4 in the boost inductance at the same current ripple For high power rated converters ≥3 kw the ccm mode of operation in 3L flying capacitor topology enables lower switching losses lower rmS current related conduction losses and easier control and emi filter design due to fixed frequency operation the combination with an interleaved approach opens the door to an even higher power density the challenges with the design of 3L flying capacitor topology include – star tup precharging and balancing of the flying ca pacitor under different operation conditions and implementing a robust gatedrive for the floating HF leg moSFets these chal lenges have been addressed in an upcoming 3 3 kw 3Lflying capacitor PFc reference design from infineon but have also been investigated widely in the literature due to the significant benefits offered by the to pology infineon is also positioning the systemsolution as a costcompetitive highperformance alternative to the tradi tional 2levelccm totem pole topology for the highest efficiency and power density in the Ac dc PFc stage Atechnology demonstrator for the 3L flying capacitor topology capable of up to 5 6 kw was built and is shown in Figure 3 two in terleaved 3level flying capacitor boost PFc legs are seen in the front the empty area in the back is reserved for an LLc dc dc con verter for downconversion to 48 Vwith each individual moSFet in HF PFc leg switching at 80 kHz the effective switching frequency of a single 3L boost stage is 160 kHz to further raise the effective frequency seen by the emi filter a second interleaved stage is used for an effective frequency of 320 kHz Aholdup extension circuit not shown allows the uti lization of more energy out of the dclink thus reducing its size the inductor with an inductance of 50 µH is realized with a rm12LP ferrite core and optimized using litz wire the power stage uses 400 V 45 mΩ imt40r045m2H Sic moSFe ts Switching frequency and inducto size can Figure 1 Application examples for coolSic 400 Vtwolevel and threelevel bidirectional totempole topology depending on the Ac voltage im age infineon technologies 13 Pcim magazine 02 2024