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International 2020 Elektronik 13 ARTIFICIAL INTELLIGENCE Fig 1 Diederik Verkest program director for machine learning at IMEC The successful tapeout of AnIA analog inference accelerator marks an important step toward validation of analog inmemory computing photo Elektronik | G Stelzer | IMEC The reference implementation not only shows that analog inmemory calculations are possible in practice but also that they achieve energy efficiency ten to a hundred times better than digital accelerators In the ML program of IMEC we attune existing and emerging memory devices to optimize them for analog inmemory computing The promising results encourage us to further develop this technology with the ambition to evolve towards 10 000 TOPS W GlobalFoundries collaborated closely with IMEC to implement the new AnIA chip using our lowpower highperformance 22FDX platform says Hiren Majmudar vice president of product management for computing and wired infrastructure at GF This test chip is a decisive step forward in demonstrating to industry how 22FDX can significantly reduce the power consumption of energyintensive AI and ML applications The 22FDX semiconductor process from GF uses 22-nm FD SOI technology to deliver outstanding performance at extremely low power with the ability to operate at 0 5 Vultralow power and with 1 pA picoamp per micron for ultralow standby leakage 22FDX with the new AiMC feature is currently in development Fig 2 on the GF 300-mm production line at fab 1 in Dresden Majmudar expects to see commercial AiMCbased products by 2022 at the latest GS To address this challenge IMEC and its industrial partners including GF have developed a new architecture industrial affiliation machine learning program that eliminates the von Neumann bottleneck by performing analog computation in SRAM cells The resulting AnIA analog inference accelerator built on the 22FDX semiconductor platform of GF has exceptional energy efficiency characterization tests showing it peaking at 2900 teraoperations per second per watt TOPS W Pattern recognition applications can thus be implemented in tiny sensors and lowpower edge devices typically conducted to date by machine learning ML in data centers These tasks can now be run locally by an energyefficient accelerator However analog implementation is not a spiking neural network where artificial neurons fire pulses Analog inmemory accelerators for ML consist of a memory array for the massively parallel analog implementation of MAC operations in the single DNN layers In addition to the SRAM cells used in the test chip resistive RAM ReRAM magnetic RAM MRAM flash memory cells or DRAM could be used The memory array contains the weights and implements the vector matix multiplication of the particular NN layer The data appears in digital form before and after processing so A Dand D Aconverters are necessary The implemented test chip has at its core 512 Kcomputer cells 1024 D Aconverters and 512 A Dconverters Including the digital infrastructure the chip produced by a 22-nm FD SOI fully depleted silicononinsulator process has a total footprint of 4 mm2 Energy efficiency 10 to 100 times better The successful tapeout of AnIA marks an important step toward validation of analog inmemory computing says Diederik Verkest program director for machine learning at IMEC Fig 1 Fig 2 Summary of performance data of AnIA from IMEC implemented in the 22FDX process of GlobalFoundries photo GlobalFoundries | IMEC