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Manufacturing power MOSFETs beginning with the 1979 HEXFET design utilized the entire silicon area for current conduction but suffered from quadratic resistance scaling at higher voltages Then in 1998 the introduction of reduced surface field RESURF architectures more commonly referred to as Superjunction technology addressed voltage scaling through 2-dimensional charge balancing enabling linear resistance scaling with breakdown voltage However these architectures sacrifice approximately 50 percent of the die area to nonconducting Pregions which are dedicated solely to voltage blocking The SuperQ design fundamentally reimagines this approach through an asymmetrical RESURF architecture that maximizes the conduction region Figure 1 Rather than relying on conventional Ppillars for charge balancing the technology uses a proprietary highaspectratio deep trench structure with sidewall charge distribution This architectural shift enables up to 95 percent of the device area to contribute to current conduction compared to 50 percent or less in tradi - tional Superjunction devices SuperQ technology achieves voltage blocking efficiency of 19-20 V μm while enabling thinner epitaxial layers with optimized doping profiles This combination results in dramatic reductions in specific onresistance RSP achieving performance that is 2 6× superior to conventional silicon at 200 Vwhile main - taining full compatibility with standard CMOS manufacturing processes on 200 mm and 300 mm wafers Figure 2 Unlike the complex epitaxial growth and implantation processes required for Superjunction devices SuperQ leverages a streamlined manufacturing flow that prioritizes both performance and costeffectiveness The platform’s scalability extends across multiple device types including diodes MOS-FETs IGBTs and power ICs covering voltage ranges from 60 Vto 1 200 V Quantified performance advantages SuperQ devices demonstrate measurable improvements across silicon MOSFET figures of merit FOM that directly impact system efficiency and thermal management In con - duction performance the 150 Vtechnology achieves onresistance as low as 2 5 mΩ in TOLL packaging matching industryleading devices while providing 1 6× improvement over nearest competitors At 200 V SuperQ devices achieve 3 7 mΩ in TOLL packaging representing nearly 50 percent reduction compared to the current industry leader and a 2 6× improvement over the nextbest com - petitor The performance advantage extends to higher voltages where traditional silicon typically cedes ground to widebandgap alternatives At 400 V SuperQ capabilities in TOLL packaging not only exceed conventional sil - icon but also outperform the industry’s best SiC devices at equivalent voltage ratings Switching performance metrics reveal equally significant advantages Switching charge QSW reduction reaches up to 2 1× com - pared to leading silicon competitors Figure 3 directly translating to faster switching times and reduced switching losses according to the following relationship This improvement enables higher switching frequencies in demanding topologies or proportional power loss reductions at equivalent frequencies Additionally SuperQ devices store significantly less energy in output capacitance COSS achieving up to 4 4× re - duction compared to silicon alternatives Re - markably even compared to industryleading GaN devices capacitive stored energy EOSS is reduced by 50 percent minimizing capa - citive switching losses governed by These combined improvements in conduction and switching performance enable system designers to achieve higher power density and efficiency while operating within familiar silicon design paradigms Manufacturing resilience and supply chain advantages The strategic importance of SuperQ technology extends beyond pure performance Figure 1 Unlike superjunctions that restrict the Nconduction region to 50 percent of the structure the SuperQ asymmetrical approach has almost no limit on the conduction area Figure 2 SuperQ vs competition in measured QSW left and EOSS parameters right Table 1 Processing requirements for SiC boules and Si ingots Images iDEAL Semimconductor 6 PCIM Magazine 02 2025